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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC145422/D
Universal Digital-Loop Transceivers (UDLT)
The MC145422 and MC145426 UDLTs are high-speed data transceivers that provide 80 kbps full-duplex data communication over 26 AWG and larger twisted-pair cable up to two kilometers in distance. Intended primarily for use in digital subscriber voice/data telephone systems, these devices can also be used in remote data acquisition and control systems. These devices utilize a 256 kilobaud modified differential phase shift keying burst modulation technique for transmission to minimize RFI/ EMI and crosstalk. Simultaneous power distribution and duplex data communication can be obtained using a single twisted-pair wire. These devices are designed for compatibility with existing, as well as evolving, telephone switching hardware and software architectures. The UDLT chip-set consists of the MC145422 Master UDLT for use at the telephone switch linecard and the MC145426 Slave UDLT for use at the remote digital telset and/or data terminal. The devices employ CMOS technology in order to take advantage of their reliable low-power operation and proven capability for complex analog/digital LSI functions. * Provides Full-Duplex Synchronous 64 kpbs Voice/Data Channel and Two 8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up to Two Kilometers * Compatible with Existing and Evolving Telephone Switch Architectures and Call Signaling Schemes * Automatic Detection Threshold Adjustment for Optimum Performance Over Varying Signal Attenuations * Protocol Independent * Single 5 V Power Supply * 22-Pin PDIP, 24-Pin SOG Packages * Application Notes AN943, AN949, AN968, AN946, and AN948 MC145422 Master UDLT * Pin Controlled Power-Down and Loopback Features * Signaling and Control I/O Capable of Sharing Common Bus Wiring with Other UDLTs * Variable Data Clock -- 64 kHz to 2.56 MHz * Pin Controlled Insertion/Extraction of 8 kbps Channel into LSB of 64 kbps Channel for Simultaneous Routing of Voice and Data Through PCM Voice Path of Telephone Switch MC145426 Slave UDLT * Compatible with MC145500 Series PCM Codec-Filters * Pin Controlled Loopback Feature * Automatic Power-Up/Power-Down Feature * On-Chip Data Clock Recovery and Generation * Pin Controlled 500 Hz D3 or CCITT Format PCM Tone Generator for Audible Feedback Applications
MC145422 MC145426
22 1
P SUFFIX PLASTIC DIP CASE 708
24 1
DW SUFFIX SOG PACKAGE CASE 751E
ORDERING INFORMATION
MC145422P MC145426P Plastic DIP Plastic DIP
MC145422DW SOG Package MC145426DW SOG Package
REV 2 9/95
(c) Motorola, Inc. 1995 MOTOROLA
MC145422*MC145426 1
PIN ASSIGNMENTS MC145422 -- MASTER (PLASTIC PACKAGE)
VSS Vref LI LB VD SI1 SO1 SI2 SO2 SE PD 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VDD LO1 LO2 RE1 Rx TDC/RDC CCI Tx TE1 SIE MSI
MC145422 -- MASTER (SOG PACKAGE)
VSS Vref LI NC LB VD SI1 SO1 SI2 SO2 SE PD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD LO1 LO2 NC RE1 Rx TDC/RDC CCI Tx TE1 SIE MSI
MC145426 -- SLAVE (PLASTIC PACKAGE)
VSS Vref LI LB VD SI1 SO1 SI2 SO2 Mu/A PD 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VDD LO1 LO2 RE1 Rx CLK X2 X1 Tx TE1 TE NC = NO CONNECTION
MC145426 -- SLAVE (SOG PACKAGE)
VSS Vref LI NC LB VD SI1 SO1 SI2 SO2 Mu/A PD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD LO1 LO2 NC RE1 Rx CLK X2 X1 Tx TE1 TE
MC145422*MC145426 2
MOTOROLA
MC145422 MASTER UDLT BLOCK DIAGRAM
+1 MODULATION BUFFER SI1 SI2 SE RE1 Rx REGISTER LB PD SIE
MODULATOR
LO1
*
LO2
-1
RECEIVE
*
DIVIDE CCI MSI SEQUENCE AND CONTROL
* *
VD CONTROL LI DEMODULATOR
VD
SO1 DEMODULATION BUFFER
*
SO2 Tx TE1 TDC/RDC
TRANSMIT REGISTER
* -- SE controlled latch
MC145426 SLAVE UDLT BLOCK DIAGRAM
SI1 SI2 Rx RE1 TONE GEN. LB TE PD X2 X1 DEMODULATOR VD CONTROL VD POWER- DOWN CONTROL OSC SEQUENCE AND CONTROL CLK REGISTER Mu/A
MODULATOR
LO1
+1
MODULATION
BUFFER
LO2
-1
LOOPBACK CONTROL
RECEIVE
LI
DEMODULATION
BUFFER
*
SO1 SO2
TRANSMIT REGISTER
Tx TE1
MOTOROLA
MC145422*MC145426 3
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Rating DC Supply Voltage Voltage, Any Pin to VSS DC Current, Any Pin (Excluding VDD, VSS) Operating Temperature Storage Temperature Symbol VDD - VSS V I TA Tstg Value - 0.5 to + 9.0 - 0.5 to VDD + 0.5 10 - 40 to + 85 - 85 to + 150 Unit V V mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range V SS (Vin or Vout) VDD. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD). Pins VDD VDD VDD MSI -- CCI TDC, RDC LO1, LO2 Min 4.5 -- -- 7.9 -- -- 64 -- Max 5.5 80 75 8.1 0.25 2.048 2560 256 Unit V mW mW kHz % MHz kHz kHz
RECOMMENDED OPERATING CONDITIONS (TA = 0 to 70C)
Parameter DC Supply Voltage Power Dissipation (PD = VDD, VDD = 5 V) Power Dissipation (PD = VSS, TE = VSS) MC145422 Frame Rate MC145422 -- MC145426 Frame Rate Slip (See Note 1) CCI Clock Frequency (MSI = 8 kHz) Data Clock Rate MC145422 Modulation Baud Rate (See Note 2)
NOTES: 1. The MC145426 crystal frequency divided by 512 must equal the MC145422 MSI Frequency 0.25% for optimum operation. 2. Assumes crystal frequency of 4.096 MHz for the MC145426 and 2.048 MHz CCI for the MC145422.
DIGITAL CHARACTERISTICS (VDD = 5 V, TA = 0 to 70C)
Parameter Input High Level Input Low Level Input Current Input Capacitance Output High Current (Except Tx on MC145422 and Tx and PD on MC145426) Output Low Current (Except Tx on MC145422 and Tx and PD on MC145426) PD Output High Current (MC145426) (See Note 1) PD Output Low Current (MC145426) (See Note 1) Tx Output High Current Tx Output Low Current Tx Input Impedance (TE1 = VSS, MC145422) Crystal Frequency (MC145426, Note 2) PCM Tone (TE = VDD, MC145426) Three-State Current (SO1, SO2, VD, Tx on MC145422, Tx on MC145426) Vref Voltage (See Note 3) X2 -- Oscillator Output High Drive Current (MC145426) (See Note 4) X2 -- Oscillator Output Low Drive Current (MC145426) (See Note 4) VOH = 4.6 V VOL = 0.4 V VOH = 2.5 V VOH = 4.6 V VOL = 0.4 V VOL = 0.8 V VOH = 2.5 V VOH = 4.6 V VOL = 0.4 V VOL = 0.8 V VOH = 2.5 V VOH = 4.6 V VOL = 0.4 V VOL = 0.8 V Except LI LI Min 3.5 -- - 1.0 - 100 -- - 1.7 - 0.36 0.36 0.8 - 90 - 10 60 100 - 3.4 - 0.7 1.7 3.5 100 4.0 - 22 -- 2 - 450 450 Max -- 1.5 1.0 100 7.5 -- -- -- -- -- -- -- -- -- -- -- -- -- 4.4 - 18 1 3 -- -- Unit V V A pF mA mA A A mA mA k MHz dBm0 A V A A
NOTES: 1. To overdrive PD from a low level to 3.5 V or a high level to 1.5 V requires a minimum of 800 A drive capability. 2. The MC145426 crystal frequency divided by 512 must equal the MC145422 MSI frequency 0.25% for optimum performance. 3. Vref typically (9/20 VDD - VSS). 4. Output drive when X1 is being driven from an external clock.
MC145422*MC145426 4
MOTOROLA
ANALOG CHARACTERISTICS (VDD = 5 V, TA = 0 to 70C)
Parameter Modulation Differential Amplitude (RL = 440 ) Modulation Differential DC Offset Demodulator Input Amplitude (See Note) Demodulator Input lmpedance LO1 to LO2 Min 4.5 0 0.050 50 Max 6.0 300 2.5 150 Unit V p-p mV V peak k
NOTE: The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to Vref.
MC145422 SWITCHING CHARACTERISTICS (VDD = 5 V, TA = 25C, CL = 50 pF)
Parameter Input Rise Time Input Fall Time Pulse Width CCI Duty Cycle Data Clock Frequency Propagation Delay Time MSI to TDC/RDC Setup Time TE1/RE1 to TDC/RDC Setup Time Rx to TDC/RDC Setup Time Rx to TDC/RDC Hold Time SI1, SI2 to MSI Setup Time SI1, SI2 to MSI Hold Time TDC/RDC MSI to SO1, SO2 VD (PD = VDD) TDC to Tx All Digital Inputs All Digital Inputs TDC/RDC, RE1, MSI Figure No. 1 1 1 1 -- 2 3 4 4 5 5 6 6 Symbol tr tf tw(H,L) tw(H,L) tDC tPLH, tPHL tsu3 tsu4 tsu3 tsu4 tsu5 th1 tsu6 th2 Min -- -- 90 45 64 -- -- 90 40 90 40 60 60 60 60 Max 4 4 -- 55 2560 90 90 -- -- -- -- -- -- -- -- Unit s s ns % kHz ns ns ns ns ns ns ns
MC145426 SWITCHING CHARACTERISTICS (VDD = 5 V, TA = 25C, CL = 50 pF)
Parameter Input Rise Time Input Fall Time Clock Output Pulse Width Crystal Frequency Propagation Delay Times TE1 Rising to CLK (TE = VDD) TE1 Rising to CLK (TE = VSS) CLK to TE1 Falling CLK to RE1 Rising RE1 Falling to CLK (TE = VDD) RE1 Falling to CLK (TE = VSS) CLK to Tx TE1 to SO1, SO2 All Digital Inputs All Digital Inputs CLK Figure No. 1 1 1 -- 7 7 7 8 8 8 9 9 5 5 6 6 Symbol tr tf tw(H,L) fX1 tp1 tp1 tp2 tp3 tp4 tp4 tp5 tp6 tsu5 th1 tsu6 th2 Min -- -- 3.8 4.086 - 50 438 -- -- - 50 438 -- -- 60 60 60 60 Max 4 4 4.0 4.1 50 538 40 40 50 538 90 90 -- -- -- -- Unit s s s MHz ns
Rx to CLK Setup Time Rx to CLK Hold Time SI1, SI2 to TE1 Setup Time SI1, SI2 to TE1 Hold Time
ns ns ns ns
MOTOROLA
MC145422*MC145426 5
SWITCHING WAVEFORMS
tw(H)
tw(L)
CLK, TDC, RDC, RE1, CCI, MSI 10%
90% 50%
50%
tr
tf
Figure 1.
70% MSI
70%
tPHL
tPLH
70% VD, SO1, SO2 30%
Figure 2.
70% TDC
70%
tPLH
tPHL
70% Tx 30%
Figure 3.
MC145422*MC145426 6
MOTOROLA
SWITCHING WAVEFORMS (continued)
70% TE1, RE1, MSI 30% tsu3 tsu4 70% TDC, RDC 30%
Figure 4.
70% TDC, RDC, CLK 30% tsu5 th1 70% 30%
70% Rx 30%
Figure 5.
tsu6 TE1 (MC145426) OR MSI (MC145422) 30% 70%
th2
70% SI1, SI2 30%
70% 30%
Figure 6.
MOTOROLA
MC145422*MC145426 7
SWITCHING WAVEFORMS (continued)
70% TE1 30% tP2 70% CLK 70%
tP1
Figure 7.
70% RE1 30%
tP3 70% CLK
tP4 70%
Figure 8.
70% Tx 30% SO1, SO2
70% 30%
tP5
tP6
70% CLK TE1
70%
Figure 9.
MC145422*MC145426 8
MOTOROLA
MC145422 MASTER UDLT PIN DESCRIPTIONS
VDD Positive Supply Normally 5 V. VSS Negative Supply This pin is the most negative supply pin, normally 0 V. Vref Reference Output This pin is the output of the internal reference supply and should be bypassed to VDD and VSS by 0.1 F capacitors. No external dc load should be placed on this pin. LI Line Input This input to the demodulator circuit has an internal 100 k resistor tied to the internal reference node so that an external capacitor and/or line transformer may be used to couple the input signal to the part with no dc offset. LB Loopback Control A low on this pin disconnects the LI pin from internal circuitry, drives LO1, LO2 to Vref and internally ties the modulator output to the demodulator input which loops the part on itself for testing in the system. The state of this pin is internally latched if the SE pin is brought and held low. Loopback is active only when PD Is high. VD Valid Data Output A high on this pin indicates that a valid line transmission has been demodulated. A valid transmission is determined by proper sync and the absence of detected bit errors. VD changes state on the leading edge of MSI when PD is high. When PD is low, VD changes state at the end of demodulation of a line transmission. VD is a standard B-series CMOS output and is high impedance when SE is held low. SI1, SI2 Signaling Bit Inputs Data on these pins is loaded on the rising edge of MSI for transmission to the slave. The state of these pins is internally latched if SE is held low. SO1, SO2 Signaling Bit Outputs These outputs are received signaling bits from the slave UDLT and change state on the rising edge of MSI if PD is high, or at the completion of demodulation if PD is low. These outputs have standard B-series CMOS drive capability and are high impedance if the SE pin is held low. SE Signal Enable Input If held high, the PD, LB, SI1, SI2, and SIE inputs and the SO1, SO2, and VD outputs function normally. If held low, the state of these inputs is latched and held internally while the outputs are high impedance. This allows these pins to be bussed with those of other UDLTs to a common controller.
PD Power-Down Input If held low, the UDLT ceases modulation. In power-down, the only active circuit is that which is necessary to demodulate an incoming burst and output the signal and valid data bits. Internal data transfers to the transmit and receive registers cease. When brought high, the UDLT powers up, and waits three positive MSI edges or until the end of an incoming transmission from the slave UDLT and begins transmitting every MSI period to the slave UDLT on the next rising edge of the MSI. MSI Master Sync Input This pin is the system sync and initiates the modulation on the twisted pair. MSI should be approximately leading-edge aligned with TDC/RDC. SIE Signal Insert Enable This pin, when held high, inserts signal bit 2 received from the slave into the LSB of the outgoing PCM word at Tx and will ignore the SI2 pin and use in place the LSB of the incoming PCM word at Rx for transmission to the slave. The PCM word to the slave will have LSB forced low in this mode. In this manner, signal bit 2 to/from the slave UDLT is inserted in to the PCM words the master sends and receives from the backplane for routing through the PABX for simultaneous voice/data communication. The state of this pin is internally latched if the SE pin is brought and held low. TE1 Transmit Data Enable 1 Input This pin controls the outputting of data on the Tx pin. While TE1 is high, the Tx data is presented on the eight rising edges of TDC/RDC. TE1 is also a high-impedance control of the Tx pin. If MSI occurs during this period, new data will be transferred to the Tx output register in the ninth high period of TDC/RDC after TE1 rises; otherwise, it will transfer on the rising edge of MSI. TE1 and TDC/RDC should be approximately leading-edge aligned. Tx Transmit Data Output This three-state output presents new voice data during the high periods of TDC/RDC when TE1 is high (see TE1). CCI Convert Clock Input A 2.048 MHz clock signal should be applied to this pin. The signal is used for internal sequencing and control. This signal should be coherent with MSI for optimum performance but may be asynchronous if slightly worse error rate performance can be tolerated. TDC/RDC Transmit/Receive Data Clock This pin is the transmit and receive data clock and can be 64 kHz to 2.56 MHz. Data is output at the Tx pin while TE1 is high on the eight rising edges of TDC/RDC after the rising edge of TE1. Data on the Rx pin is loaded into the receive register of the UDLT on the eight falling edges of TDC/RDC after a positive transition on RE1. This clock should be approximately leading-edge aligned with MSI.
MOTOROLA
MC145422*MC145426 9
Rx Receive Data Voice data is clocked into the UDLT from this pin on the falling edges of TDC/RDC under the control of RE1. RE1 Receive Data Enable 1 Input A rising edge on this pin will enable data on the Rx pin to be loaded into the receive data register on the next eight falling edges of the data dock, TDC/RDC. RE1 and TDC/RDC should be approximately leading-edge aligned. LO1, LO2 Line Driver Outputs These outputs drive the twisted pair line with 256 kHz modified DPSK bursts each frame and are push-pull. These pins are driven to Vref when not modulating the line.
SI1, SI2 Signaling Bit Inputs Data on these pins is loaded on the rising edge of TE1 for transmission to the master. If no transmissions from the master are being received and PD is high, data on these pins will be loaded into the part on an internal signal. Therefore, data on these pins should be steady until synchronous communication with the master has been established, as indicated by the high on VD. SO1, SO2 Signaling Bit Outputs These outputs are received signaling bits from the master UDLT and change state on the rising edge of TE1. These outputs have standard B-series CMOS output drive capability. PD Power-Down Input/Output This is a bidirectional pin with weak output drivers such that it can be overdriven externally. When held low, the UDLT is powered down and the only active circuitry is that which is necessary for demodulation, TE1/RE1/CLK generation upon demodulation, the outputting of data received from the master, and updating of VD status. When held high, the UDLT is powered up and transmits in response to transmissions from the master. If no received bursts from the master have occurred when powered up for 250 s (derived from the internal oscillator frequency), the UDLT will generate a free running 125 s internal clock from the internal oscillator and will burst a transmission to the master every other internal 125 s clock using data on the SI1 and SI2 pins and the last data word loaded into the receive register. The weak output drivers will try to force PD high when a transmission from the master is demodulated and will try to force it low if 250 s have passed without a transmission from the master. This allows the slave UDLT to self power-up and down in demand powered loop systems. TE Tone Enable A high on this pin generates a 500 Hz square wave PCM tone and inserts it in place of the demodulated voice PCM word from the master for outputting to the Tx pin to the telset mono-circuit. A high on TE will generate TE1 and CLK from the internal oscillator when the slave is not receiving bursts from the master so that the PCM square wave can be loaded into the codec-filter. This feature allows the user to provide audio feedback for the telset keyboard depressions except during loopback. During loopback of the slave UDLT, CLK is defeated so a tone cannot be generated in this mode. TE1 Transmit Data Enable 1 Output This is a standard B-series CMOS output which goes high after the completion of demodulation of an incoming transmission from the master. It remains high for 8 CLK periods and then low until the next burst from the master is demodulated. While high, the voice data just demodulated is output on the first eight rising edges of CLK at the Tx pin. The signaling data just demodulated is output on SO1 and SO2 on TE1's rising edge, as is VD.
MC145426 SLAVE UDLT PIN DESCRIPTIONS
VDD Positive Supply Normally 5 V. VSS Negative Supply This pin is the most negative supply pin, normally 0 V. Vref Reference Output This pin is the output of the internal reference supply and should be bypassed to VDD and VSS by 0.1 F capacitors. No external dc load should be placed on this pin. LI Line Input This input to the demodulator circuit has an internal 100 k resistor tied to the internal reference node (Vref) so that an external capacitor and/or line transformer may be used to couple the signal to this part with no dc offset. LB Loopback Control When this pin is held low and PD is high (the UDLT is receiving transmissions from the master), the UDLT will use the 8 bits of demodulated PCM data in place of the 8 bits of Rx data in the return burst to the Master, thereby looping the part back on itself for system testing. SI1 and SI2 operate normally in this mode. CLK will be held low during loopback operation. VD Valid Data Output A high on this pin indicates that a valid line transmission has been demodulated. A valid transmission is determined by proper sync and the absence of detected bit errors.VD changes state on the leading edge of TE1. If no transmissions from the master have been received in the last 250 s (derived from the internal oscillator), VD will go low without TE1 rising since TE1 is not generated in the absence of received transmissions from the master (see TE pin description for the one exception to this).
MC145422*MC145426 10
MOTOROLA
Tx Transmit Data Output This is a standard B-series CMOS output. Voice data is output on this pin on the rising edges of CLK while TE1 is high and is high impedance when TE1 is low. X1 Crystal Input A 4.096 MHz crystal is tied between this pin and X2. A 10 M resistor across X1 and X2 and 25 pF capacitors from X1 and X2 to VSS are required for stability and to ensure startup. X1 may be driven by an external CMOS clock signal if X2 is left open. X2 Crystal Output This pin is capable of driving one external CMOS input and 15 pF of additional capacitance (see X1 pin description). CLK Clock Output This is a standard B-series CMOS output which provides the data clock for the telset codec-filter. It is generated by dividing the oscillator down to 128 kHz and starts upon the completion of demodulation of an incoming burst from the master. At this time, CLK begins and TE1 goes high. CLK will remain active for 16 periods, at the end of which it will remain low until another transmission from the master is demodulated. In this manner, sync from the master is established in the slave and any clock slip between the master and the slave is absorbed each frame. CLK is generated in response to an incoming burst from the master, however, if TE is brought high, then CLK and TE1/RE1 are generated from the internal oscillator until TE is brought low or an incoming burst from the master is received. CLK is disabled when LB is held low. Rx Receive Data Input Voice data from the telset codec-filter is input on this pin on the first eight falling edges of CLK after RE1 goes high. Mu/A Tone Digital Format Input This pin determines if the PCM code of the 500 Hz square wave tone, when TE is high, is Mu-Law (Mu/A = 1) or A-Law (Mu/A = 0) format. RE1 Receive Data Enable 1 Output This is a standard B-series CMOS output which is the inverse of TE1 (see TE1 pin description). LO1, LO2 Line Driver Outputs These outputs drive the twisted pair line with 256 kHz modified DPSK bursts each frame and are push-pull. These pins are driven to Vref when the device is not modulating.
BACKGROUND
The MC145422 master and MC145426 slave UDLT transceiver ICs main application is to bidirectionally transmit the digital signals present at a codec-filter digital-PABX backplane interface over normal telephone wire pairs. This allows the remoting of the codec-filter in a digital telephone set and enables each set to have a high speed data access to the PABX switching facility. In effect, the UDLT allows each PABX subscriber direct access to the inherent 64 kbps data routing capabilities of the PABX. The UDLT provides a means for transmitting and receiving 64 kbits of voice data and 16 kbps of signaling data in two- wire format over normal telephone pairs. The UDLT is a two- chip set consisting of a master and a slave. The master UDLT replaces the codec-filter and SLIC on the PABX line card, and transmits and receives data over the wire pair to the teleset. The UDLT appears to the linecard and backplane as if it were a PCM Codec-Filter and has almost the same digital interface features as the MC145500 series codec-filters. The slave UDLT is located in the telset and interfaces the codec-filter to the wire pair. By hooking two UDLTs back- to-back, a repeater can also be formed. The master and slave UDLTs operate in a frame synchronous manner, sync being established at the slave by the timing of the master's transmission. The master's sync is derived from the PABX frame sync. The UDLT operates using one twisted pair. Eight bits of voice data and two bits of signaling data are transmitted and received each frame in a half-duplex manner (i.e., the slave waits until the transmission from the master is completely received before transmitting back to the master). Transmission occurs at 256 kHz bit rate using a modified form of DPSK. This "ping- pong" mode will allow transmission of data at distances up to two kilometers before turnaround delay becomes a problem. The UDLT is so defined as to allow this data to be handled by the linecard, backplane, and PABX as if it were just another voice conversation. This allows existing PABX hardware and software to be unchanged and yet provides switched 64 kbps voice or data communications throughout its service area by simply replacing a subscriber's linecard and teleset. A feature in the master allows one of the two signaling bits to be inserted and extracted from the backplane PCM word to allow simultaneous voice and data transmission through the PABX. Both UDLTs have a loopback feature by which the device can be tested in the user system. The slave UDLT has the additional feature of providing a 500 Hz Mu-Law or A-Law coded square wave to the codec- filter when the TE pin is brought high. This can be used to provide audio feedback in the telset during keyboard depressions.
CIRCUIT DESCRIPTION
GENERAL The UDLT consists of a modulator, demodulator, two intermediate data buffers, sequencing and control logic, and transmit and receive data registers. The data registers interface to the linecard or codec-filter digital interface signals, the modulator and demodulator interface the twisted pair transmission medium, while the intermediate data registers buffer data between these two sections. The UDLT is
MOTOROLA
MC145422*MC145426 11
intended to operate on a single 5 V supply and can be driven by TTL or CMOS logic. MASTER OPERATION In the master, data from the linecard is loaded into the receive register each frame from the Rx pin under the control of the TDC/RDC clock and the receive data enable, RE1. RE1 controls loading of eight serial bits, henceforth referred to as the voice data word. Each MSI, these words are transferred out of the receive register to the modulation buffer for subsequent modulation onto the line. The modulation buffer takes the receive voice data word and the two signaling data input bits on SI1 and SI2 loaded on the MSI transition and formats the 10 bits into a specific order. This data field is then transmitted in a 256 kHz modified DPSK burst onto the line to the remote slave UDLT. Upon demodulating the return burst from the slave, the decoded data is transferred to the demodulation buffer and the signaling bits are stripped ready to be output on SO1 and SO2 at the next MSI. The voice data word is loaded into the transmit register as described in the TE1 pin description for outputting via the Tx pin at the TDC/RDC data clock rate under the control of TE1. VD is output on the rising edge of MSI. Timing diagrams for the master are shown in Figure 10. SLAVE OPERATION In the slave, the synchronizing event is the detection of an incoming line transmission from the master as indicated by the completion of demodulation. When an incoming burst from the master is demodulated, several events occur. As in the master, data is transferred from the demodulator to the demodulation buffer and the signaling bits are stripped for outputting at SO1 and SO2. Data in the receive register is transferred to the modulation buffer. TE1 goes high loading in data at SI1 and SI2, which will be used in the transmission burst to the master along with the data in the transmit data buffer, and outputting SO1, SO2, and VD. Modulation of the burst begins four 256 kHz periods after the completion of demodulation. While TE1 is high, voice data is output on Tx to the telset codec-filter on the rising edges of the data clock output on the CLK pin. On the ninth rising edge of CLK, TE1 goes low, RE1 goes high, and voice data from the codec-filter is input to the receiver register from the Rx pin on the next eight falling edges of CLK. RE1 is TE1 inverted and is provided to facilitate interface to the codec-filter.
The CLK pin 128 kHz output is formed by dividing down the 4.096 MHz crystal frequency by 32. Slippage between the frame rate of the master (as represented by the completion of demodulation of an incoming transmission from the master) and the crystal frequency is absorbed by holding the 16th low period of CLK until the next completion of demodulation. This is shown in the slave UDLT timing diagram of Figure 11. POWER-DOWN OPERATION In the master when PD is low, the UDLT stops modulating and only that circuitry necessary to demodulate the incoming bursts and output the signaling and VD data bits is active. In this mode, if the UDLT receives a burst from the slave, the SO1, SO2, and VD pins will change state upon completion of the demodulation instead of the the rising edge of MSI. The state of these pins will not change until either three rising MSI edges have occurred without the reception of a burst from the slave or until another burst is demodulated, whichever occurs first. When PD is brought high, the master UDLT will wait either three rising MSI edges or until the MSI rising edge following the demodulation of an incoming burst before transmitting to the slave. The data for the first transmission to the slave after power-up is loaded into the UDLT during the RE1 period prior to the burst in the case of voice, and on the present rising edge of MSI for signaling data. In the slave, PD is a bidirectional pin with weak output drivers such that it can be overdriven externally. When held low, the UDLT slave is powered-down and only that circuitry necessary for demodulation, TE1/RE1/CLK generation upon demodulation, and the outputting of voice and signaling bits is active. When held high, the UDLT slave is powered-up and transmits normally in response to transmissions from the master. If no bursts have been received from the master within 250 s after power-up (derived from the internal oscillator frequency), the UDLT generates an internal 125 s free-running clock from the internal oscillator. The slave UDLT then bursts a transmission to the master UDLT every other 125 s clock period using data loaded into the Rx pin during the last RE1 period and SI1, SI2 data loaded in on the internal 125 s clock edge. The weak output drivers will try to force PD high when a transmission from the master is demodulated and will try to force it low if 250 s have passed without a transmission from the master. This allows the slave UDLT to self power-up and down in demand power-loop systems.
MC145422*MC145426 12
MOTOROLA
125 s MSI IN
CCI/TDC/RDC
***
IN
TE1 THREE-STATE
IN
Tx RE1
OUT IN
Rx
VALID DATA
DON'T CARE **
IN
SI1, SI2
VALID
****************************************************** DON'T CARE ******************************************************
VALID
IN
SO1, SO2
OUT
VD
OUT
DEMODULATOR SYNC OUT (INTERNAL)
TRANSFER RECEIVE REGISTER TO MODULATION BUFFER, LATCH VALID DATA PIN, LATCH SI1, SI2. TWO CCI CLOCKS LATER, TRANSFER RECEIVE REGISTER TO MODULATION BUFFER, START MODULATION.
TRANSFER DEMODULATOR DATA TO DEMODULATION BUFFER
Figure 10. Master UDLT Timing
MOTOROLA
MC145422*MC145426 13
125 s DEMODULATOR SYNC (INTERNAL) CLK (128 kHz)
INTERNAL 2.048 MHz FROM XTAL TE1
*
* * * * * * * ** ** ** * * * * * *
NOTE 1
***
***
* * * * * * * ** ** ** * * * * * *
***
RE1 VOICE Tx HIGH IMPEDANCE
Rx
DON'T CARE
VOICE
SI1, SI2
DON'T CARE
SO1, SO2
VD TRANSFER DEMODULATION BUFFER TO TRANSMIT REGISTER, GENERATE ENABLES, LATCH SI1, SI2, OUTPUT Tx, SO1, SO2, OUTPUT VALID DATA, START 128 kHz CLOCK, START MODULATION AFTER FOUR 256 kHz BAUD PERIODS. DEMODULATION DATA TRANSFER TO DEMODULATION BUFFER NOTE: 1. Slip between master and slave is taken up in this period.
Figure 11. Slave UDLT Timing
MC145422*MC145426 14
MOTOROLA
Both the Differential-Phase Shift Keying and the Modified Differential-Phase-Shift Keying waveforms are shown in Figures 12 thru 14. The DPSK encodes data as phase reversals of a 256 kHz carrier. A 0 is indicated by a 180 phase shift between bit boundaries, while the signal continues in phase to indicate a 1. This method needs no additional bits to indicate the start of the burst. The modified DPSK waveform actually used in the transceivers is a slightly modified form of DPSK, as shown in Figure 12. The phase-reversal cusps of the DPSK waveform have been replaced by a 128 kHz half-cycle to lower the
spectral content of the waveform, which, save for some key differences, appears quite similar to frequency shift keying. The burst always begins and ends with a half-cycle of 256 kHz, which helps locate bit boundaries. The bit pattern shown in Figure 13a shows a stable waveform due to the even number of phase changes or zeros. The waveform shown in Figure 13b shows random data patterns being modulated. Figure 14 shows the "ping-pong" signals on 3000 feet of 26 AWG twisted-pair wire as viewed at LI of the master UDLT and the slave UDLT.
DIFFERENTIAL-PHASE-SHIFT KEYING
MODIFIED DIFFERENTIAL-PHASE-SHIFT KEYING
1
0
1
0
1
0
1
0
0
1
Figure 12. Modified Differential Phase Shift Keying
13a. Bit Pattern -- 1010101000
13b. Bit Pattern -- Random
Figure 13. Typical Signal Waveforms at Demodulator
MOTOROLA
MC145422*MC145426 15
MASTER
SLAVE
BIT PATTERN -- 1010101000
BIT PATTERN -- RANDOM
Figure 14. Typical Signal Waveforms at Demodulator
MC145422*MC145426 16
MOTOROLA
MOTOROLA
POWER SUPPLY TIP 110 110 8 kHz FRAME SYNC TRANSMIT DATA BUS RECEIVE DATA BUS 2.048 MHz DATA CLOCK N = 0.5 110 110 N=2 0.1 F 0.1 F N = 0.5 N=4 MC145422 5.1 k 5.1 k RING 22 21 2 20 3 6 8 7 9 5 4 12 V DD MSI LO1 Tx 15 Vref Rx 18 LO2 T/RDC 17 16 LI CCI SI1 PD 11 19 SI2 RE1 14 SO1 TE1 13 SO2 SIE 10 VD SE VSS 1 LB POWER SUPPLY TIMING AND CONTROL 110 110 TIP
TO BACKPLANE
TO BACKPLANE
Figure 15. Typical Multichannel Digital Line Card
N = 0.5 110 110 N=2 0.1 F 0.1 F N = 0.5 RING N=4 5.1 k 5.1 k 22 21 2 20 3 6 8 7 9 5 4 12 V DD MSI LO1 Tx 15 Vref Rx 18 LO2 T/RDC 17 16 LI CCI 11 SI1 PD 19 SI2 RE1 14 SO1 TE1 13 SO2 SIE 10 VD SE 1 VSS LB MC145422
MC145422*MC145426 17
10 V 10 V 5V 5V 4.7 k T1 N = 0.5 4.7 k VDD Mu/A RCE PD LB LI Vref UDLT MC145426 VD LO1 LO2 Mu/A SI1 VSS 1 8 110 10 N=2 110 RING N = 0.5 20 110 21 110 5 2 3 N=4 4 11 Rx RE1 CLK SI2 TE SO1 SO2 X1 X2 19 17 8 12 7 9 15 100 k 4.096 MHz 20 pF 100 k DTMF OUT OPL OH/T TSO MO MS OSCin OSCout 9 3.579545 MHz 8 0.1 F 10 47 k 4.7 F 1.8 k 11 7 PULSE/TONE DIALER 12 10 V SPEAKER LM317 270 5V 4.7 F 78M05 33 V 2W 17 10 k 18 10 V 50 F 20 pF 20 10 M 18 18 PD Tx- 14 TE1 13 VDD 11 RDD 15 14 Tx 22 10 k 16 6 7 5 56 k 4 2 3 1 5V 3.6 k 1.6 k
0.1 F
MC145422*MC145426 18
TDD 10 MONOTDE 12 CIRCUIT TxI MC145503 TDC 13 RxO RDC 9 V LS Tx+ 8 VSS VAG S1B OPEN = ON HOOK +5V
XMTR
TIP
RCVR
VAG VAG S1A CLOSED = ON HOOK
Figure 16. Basic Digital Telset
1 VDD
3 COL1
4
COL2
5
COL3
2
COL4
16 ROW1 15 ROW2
14 ROW3
13 ROW4
6 VSS
= ANALOG GROUND
MOTOROLA
= DIGITAL GROUND
MOTOROLA
10 V 10 k -5V +5V 10 F 1 C13 TE TE1 Tx X1 16 X2 20 pF R1 10 M 14 15 Y1 4.096 MHz 13 Vref 2 VAG R5 3 RxO RxG RxO C2 +Tx 20 pF 4 5 6 R7 10 k MC145502 5 k R6 500 R8 56 k C1 S2 - SW112 PD Mu/A SO2 SI2 SO1 SI1 VD LB MC145426 11 10 9 8 7 6 5 4 NC R3 5 k +5V R2 10 k S3 3 LI 22 5k VDD V ref 2 +5V VSS 1 0.1F C9 0.1 F 110 D3 R10 110 D4 N=2 110 D5 D6 R9 110 C8 N=1 D2 +5V D1 R11 T1 5 k N=4 SPEAKER 10 F 11 VSS -5V C12 7 TxI 8 -Tx 9 Mu/A 10 PDI 22 RSI VDD 21 20 RDD 19 RCE 18 RDC 17 TDC 16 CCI 15 TDD 14 TDE 13 MSI VLS 12 17 CLK 18 Rx 19 RE1 20 LO2 21 LO1 HOOK SWITCH TIP RING
VAG
0.1 F R13
C4
10 k
1 k R12
Figure 17. Full-Featured Digital Telset
+5V
= ANALOG GROUND
= DIGITAL GROUND
MC145422*MC145426 19
PACKAGE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 708-04
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 27.56 28.32 8.64 9.14 3.94 5.08 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.38 2.92 3.43 10.16 BSC 15 0 1.02 0.51 INCHES MIN MAX 1.085 1.115 0.340 0.360 0.155 0.200 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.015 0.115 0.135 0.400 BSC 15 0 0.020 0.040
22
12
B
1 11
A N
L
C K
H
G
F
D
SEATING PLANE
M
J
DIM A B C D F G H J K L M N
DW SUFFIX SOG PACKAGE CASE 751E-04 -A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC145422*MC145426 20
*MC145422/D*
MC145422/D MOTOROLA

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